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rf amplifier 1.7ghz to 2.2 ghz F1421 datasheet ? 2018 integrated device technology, inc. 1 rev o may 11 , 2018 description the F1421 is a high gain / high linearity rf amplifier used in high- performance rf applications. the F1421 provides 20.3db gain with a +4 0dbm oip3 and 5.5 db noise figure at 1.9ghz. this device uses a single 5v supply and 138 ma of i cc . in typical base stations, rf amplifiers are used in the rx and tx traffic paths to boost signal levels. the F1421 amplifier offers very high reliability due to its construction using silicon die in a qfn package. typical applications ? multi-mode, multi-carrier transmitters ? pcs1900 base stations ? dcs1800 base stations ? wimax and lte base stations ? umts/wcdma 3g base stations ? phs/pas base stations ? public safety infrastructure features ? broadband 1.7 ghz to 2.2ghz ? 20. 3db typical gain at 1.9ghz ? 5.5 db noise figure at 1.9ghz ? +4 0dbm oip3 at 1.9ghz ? +2 3dbm output p1db at 1.9ghz ? single 5v supply voltage ? i cc = 1 38 ma ? -40c to +105c operating temperature ? 50 ? single -ended input / output impedances ? standby mode for power savings ? 4mm x 4mm, 24-pin qfn package block diagram figure 1. block diagram zero-distortion tm rfin rfout stby v cc
? 2018 integrated device technology, inc. 2 rev o may 11 , 2018 F1421 datasheet pin assignments figure 2. pin assignments for 4mm x 4mm x 0.9mm qfn package C top view nc nc nc nc nc nc ncnc gnd gnd rfout nc nc rset rdset nc v cc stby nc rfin gnd nc nc gnd epad 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 control circuit pin descriptions table 1. pin descriptions number name description 1 - 7, 12, 16 - 20 , 24 nc no internal connection. these pins can be left unconnected, have a voltage applied, or be connected to ground (recommended). 8 stby standby (high = device power off, low/open = device power on). internally this pin has a pull -down resistor that is connected to gnd. 9 rset amplifier bias current setting resistor. connect a 2.26k? resistor to ground. 10 rdset amplifier second bias current setting resistor. connect a 5.76k? resistor to ground. 11 v cc power supply for the amplifier. 13, 15, 21, 23 gnd internally grounded. th ese pins must be grounded as close to the device as possible. 14 rfout rf output. must use an external dc block as close to the pin as possible. 22 rfin rf input internally matched to 50. must use an external dc block. the dc block should be placed as close to the pin as possible for best rf performance. C epad exposed paddle. internally connected to ground. solder this exposed paddle to a printed circuit board (pcb) pad that uses multiple ground vias to provide heat transfer out of the device into the pcb ground planes. these multiple ground vias are also required to ac hieve the specified rf performance.
? 2018 integrated device technology, inc. 3 rev o may 11 , 2018 F1421 datasheet absolute maximum ratings the absolute maximum ratings are stress ratings only. stresses greater than those listed below can cause permanent damage to the device. functional operation of the F1421 at absolute maximum ratings is not implied. exposure to absolute maximum rating conditions may affect device reliability. table 2. absolute maximum ratings parameter symbol minimum maximum units supply voltage v cc - 0.3 +5.5 v stby v stby - 0.3 v cc + 0.25 v rfin externally applied dc voltage v rfin - 0.3 + 0.3 v rfout externally applied dc voltage v rfout v cc - 0.15 v cc + 0.15 v maximum rf cw input power p max_in +18 dbm continuous power dissipation p diss 1.5 w junction temperature t jmax +150 c storage temperature range t stor - 65 +150 c lead temperature (soldering, 10s) t lead +260 c electrostatic discharge C hbm (jedec/esda js- 001 -2012) v esdhmb 2000 (class 2) v electrostatic discharge C cdm (jedec 22-c101f) v esdcdm 500 (class c2) v
? 2018 integrated device technology, inc. 4 rev o may 11 , 2018 F1421 datasheet recommended operating conditions table 3. recommended operating conditions parameter symbol condition minimum typical maximum units supply voltage v cc 4.75 5.25 v operating temperature range t ep exposed paddle - 40 +105 c rf frequency range f rf operating range 1.7 2.2 g hz maximum operating in put rf power [a] p in _max + 10 dbm rf source impedance z rfi single ended 50 rf load impedance z rfo single ended 50 [a] input / output load impedance < 2:1 vswr any phase based in a 50? system.
? 2018 integrated device technology, inc. 5 rev o may 11 , 2018 F1421 datasheet electrical characteristics see the F1421 typical application circuit. specifications apply when operated at v cc = +5.0v, f rf = 1.9ghz, t ep = +25c, z s = z l = 50 ? , tone spacing = 5mhz, p out = +4dbm/tone, evaluation board (evkit) traces and connectors are de-embedded, unless otherwise stated. table 4. electrical characteristics parameter symbol condition minimum typical maximum units logic input high threshold v ih 1.1 [a] v cc v logic input low threshold v il 0.8 v logic current i il, i ih, standby pin - 10 10 a supply current i cc standby = low or open 1 38 153 ma i cc_stby standby = high 0.6 1.2 ma gain g 1.7 f rf = 1.7g hz 19. 6 db g 1 .9 f rf = 1.9ghz 18.8 20. 3 21.8 g 2.2 f rf = 2.2g hz 21. 0 input return loss rl in 15 db output return loss rl out 15 db gain flatness g flat f rf = 1.7g hz to 2.2ghz 1.3 db gain ripple g ripple in any 20mhz range over rf band 0 .0 6 db noise figure nf f rf = 1.7g hz 5.6 db f rf = 1.9ghz 5.5 f rf = 2.2g hz 5.6 f rf = 1.9ghz, t ep =+105c 6. 3 output third order intercept point oip3 p out = +4dbm/tone 5mhz tone delta 36 40 dbm output 1db compression op1db 21 23 dbm power on switching time t on 50% stby control to within 0.2db of the on state final gain value 120 ns power off switching time t off 50% stby control to 30db below on state gain value 80 ns [a] specifications in the minimum/maximum columns that are shown in bold italics are guaranteed by test. specifications in these columns that are not shown in bold italics are guaranteed by design characterization.
? 2018 integrated device technology, inc. 6 rev o may 11 , 2018 F1421 datasheet thermal characteristics table 5. package thermal characteristics parameter symbol value units junction to ambient thermal resistance ja 45 c/w junction to case thermal resistance (case is defined as the exposed paddle) jc -bot 36 c/w moisture sensitivity rating (per j-std-020) msl 1 typical operating conditions (toc) ? v cc = 5.0v ? z l = z s = 50 ? single ended ? f rf = 1.9ghz ? t ep = 25 oc (all temperatures are referenced to the exposed paddle) ? stby = low (0v) ? p out = +4dbm/tone ? 5mhz tone spacing ? evaluation kit traces and connector losses are de-embedded
? 2018 integrated device technology, inc. 7 rev o may 11 , 2018 F1421 datasheet typical performance characteristics figure 3. gain vs frequency figure 4. reverse isolation vs frequency figure 5. input return loss vs frequency figure 6. output return loss vs frequency figure 7. gain vs frequency figure 8. stability vs frequency 0 5 10 15 20 25 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 gain (db) frequency (ghz) +4.75 v / -40 c +4.75 v / +25 c +4.75 v / +105 c +5.00 v / -40 c +5.00 v / +25 c +5.00 v / +105 c +5.25 v / -40 c +5.25 v / +25 c +5.25 v / +105 c -50 -45 -40 -35 -30 -25 -20 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 isolation (db) frequency (ghz) +4.75 v / -40 c +4.75 v / +25 c +4.75 v / +105 c +5.00 v / -40 c +5.00 v / +25 c +5.00 v / +105 c +5.25 v / -40 c +5.25 v / +25 c +5.25 v / +105 c -30 -25 -20 -15 -10 -5 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 return loss (db) frequency (ghz) +4.75 v / -40 c +4.75 v / +25 c +4.75 v / +105 c +5.00 v / -40 c +5.00 v / +25 c +5.00 v / +105 c +5.25 v / -40 c +5.25 v / +25 c +5.25 v / +105 c -30 -25 -20 -15 -10 -5 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 return loss (db) frequency (ghz) +4.75 v / -40 c +4.75 v / +25 c +4.75 v / +105 c +5.00 v / -40 c +5.00 v / +25 c +5.00 v / +105 c +5.25 v / -40 c +5.25 v / +25 c +5.25 v / +105 c 15 16 17 18 19 20 21 22 23 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 gain (db) frequency (ghz) +4.75 v / -40 c +4.75 v / +25 c +4.75 v / +105 c +5.00 v / -40 c +5.00 v / +25 c +5.00 v / +105 c +5.25 v / -40 c +5.25 v / +25 c +5.25 v / +105 c 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 stability factor frequency (ghz) +4.75 v / -40 c +4.75 v / +25 c +4.75 v / +105 c +5.00 v / -40 c +5.00 v / +25 c +5.00 v / +105 c +5.25 v / -40 c +5.25 v / +25 c +5.25 v / +105 c
? 2018 integrated device technology, inc. 8 rev o may 11 , 2018 F1421 datasheet typical performance characteristics figure 9. output ip3 versus frequency figure 10 . output p1db versus frequency figure 11 . second harmonic versus frequency figure 12 . third harmonic versus frequency figure 13 . noise figure versus frequency figure 14 . standby switching speed 30 32 34 36 38 40 42 44 46 48 50 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 output ip3 (dbm) frequency (ghz) +4.75 v / -40 c +4.75 v / +25 c +4.75 v / +105 c +5.00 v / -40 c +5.00 v / +25 c +5.00 v / +105 c +5.25 v / -40 c +5.25 v / +25 c +5.25 v / +105 c 15 16 17 18 19 20 21 22 23 24 25 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 output p1db (dbm) frequency (ghz) +4.75 v / -40 c +4.75 v / +25 c +4.75 v / +105 c +5.00 v / -40 c +5.00 v / +25 c +5.00 v / +105 c +5.25 v / -40 c +5.25 v / +25 c +5.25 v / +105 c -90 -85 -80 -75 -70 -65 -60 -55 -50 -45 -40 -35 -30 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 harmonic (dbc) frequency (ghz) +4.75 v / -40 c +4.75 v / +25 c +4.75 v / +105 c +5.00 v / -40 c +5.00 v / +25 c +5.00 v / +105 c +5.25 v / -40 c +5.25 v / +25 c +5.25 v / +105 c -90 -85 -80 -75 -70 -65 -60 -55 -50 -45 -40 -35 -30 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 harmonic (dbc) frequency (ghz) +4.75 v / -40 c +4.75 v / +25 c +4.75 v / +105 c +5.00 v / -40 c +5.00 v / +25 c +5.00 v / +105 c +5.25 v / -40 c +5.25 v / +25 c +5.25 v / +105 c 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 noise figure (db) frequency (ghz) +4.75 v / -45 c +4.75 v / +20 c +4.75 v / +100 c +5.00 v / -45 c +5.00 v / +20 c +5.00 v / +100 c +5.25 v / -45 c +5.25 v / +20 c +5.25 v / +100 c -30 -25 -20 -15 -10 -5 0 5 10 15 20 -20 0 20 40 60 80 100 120 140 160 180 power (dbm) time (ns) stby off to on stby on to off rf power is calculated by 20 log (envelope of rf voltage). voltage dynamic range limits power dynamic range to about 30 db.
? 2018 integrated device technology, inc. 9 rev o may 11 , 2018 F1421 datasheet evaluation kit picture note: the evaluation board is used for multiple devices. figure 15 . top view figure 16 . bottom view
? 2018 integrated device technology, inc. 10 rev o may 11 , 2018 F1421 datasheet evaluation kit / applications circuit figure 17 . electrical schematic
? 2018 integrated device technology, inc. 11 rev o may 11 , 2018 F1421 datasheet table 6. bill of material (bom) part reference qty description m anu factur er part # m anu factur er c1 2 2.2pf 0.1, 50v, c0g ceramic capacitor (0402) grm1555c1h2n2 0j murata c4 2 4.0pf 0.1, 50v, c0g ceramic capacitor (0402) grm1555c1h470j murata c7 1 2pf 0.1pf, 50v, c0g ceramic capacitor (0402) grm1555c1h2r0b murata c8 1 1000pf 5%, 50v, c0g ceramic capacitor (0402) grm1555c1h102j murata c9 1 0.1f 10%, 16v, x7r ceramic capacitor (0402) grm155r71c104k murata c10 1 10f 20%, 16v, x6s ceramic capacitor (0603) grm188c81c106m murata r1 1 1.87 k 1%, 1/10w, resistor (0402) erj -2rkf2 00 1x panasonic r2 1 5.11 k 1%, 1/10w, resistor (0402) erj -2rkf340 1x panasonic r3 1 1k 1%, 1/10w, resistor (0402) erj -2rkf1001x panasonic c3, c6, r4 3 0 resistors (0402) erj -2ge0r00x panasonic j4 1 conn header vert sgl 2 x 1 pos gold 961102 - 6404 - ar 3m j5 1 conn header vert sgl 3 x 1 pos gold 961103 - 6404 - ar 3m j1, j2, j3 3 edge launch sma (0.375 inch pitch ground, tab) 142 -0701- 851 emerson johnson u1 1 amp F1421 nlgk idt 1 printed circuit board f1420 evk it rev 1 idt c2, c5 dnp
? 2018 integrated device technology, inc. 12 rev o may 11 , 2018 F1421 datasheet evaluation kit operation power supply setup set up a power supply in the voltage range of 3.0v to 5.25v with the power supply output disabled. the voltage can be applied via one of the fol lowing connections (see figure 18 ): ? j3 connector ? j4 header connection (gnd is the pin farthest away from the j4 label) figure 18 . power supply connections standby (stby) pin the evaluation board has the ability to control the F1421 for standby operation . the logic voltage is applied to the j5 header connection as shown in figure 19 . to place the amplifier in the active mode (on) use one of these options : ? make no connections on j5 ? apply a logic low signal to stby (pin 2 of j5 or the middle pin). ? make a connection between pin 3 (gnd) and pin 2 (stby, the middle pin) of j5. to place the amplifier in the standby mode (off), use one of these options: ? apply a logic high signal to the stby (pin 2 of j5 or the middle pin). ? make a connection between pin 1 (vcc) and pin 2 (stby, the middle pin) of j5. figure 19 . standby pin connection
? 2018 integrated device technology, inc. 13 rev o may 11 , 2018 F1421 datasheet power-on procedure set up the voltage supplies and evaluation board as described in the "power supply setup" section with the " standby pin set for logic low. ? enable the power supply. ? the stby pin now can now be exercised. power-off procedure ? set the stby pin to logic low. ? disable the power supply. application information the F1421 has been optimized for use in high-performance rf applications from 1.7ghz to 2.2g hz. standby mode (stby) the F1421 has a standby pin which allows the amplifier to be turned off to decrease overall power requirements. the pin uses simple logic levels and is compatible with both jedec 1.8v and jedec 3.3v logic. table 7 list s the amplifier state for the logic. an internal pull-down resistor causes the amplifier to default to the on state. table 7. standby truth table stby (pin 8) condition low or open amplifier on high amplifier off rset and rdset the F1421 has been optimized for gain and intermodulation products by adjust ing the bias resistors rset and rdset. for the optimized setting , rset (r1) is 1. 87 k and rdset (r2) is 5.11 k . power supplies the power supply pin should be bypassed with external capacitors to minimize noise and fast transients. supply noise can degra de the noise figure , and fast transients can trigger esd clamps and cause them to fail. supply voltage changes or transients should h av e a slew rate less than 1v/ 20s.
? 2018 integrated device technology, inc. 14 rev o may 11 , 2018 F1421 datasheet control pin interface if control signal integrity is a concern and clean signals cannot be guaranteed due to overshoot, undershoot, ringing, etc., the followin g circuit at the input of each control pin is recommended. this applies to control pin 8 (stby). note the recommended resistor and capacitor values do not necessarily match the evk it bom for the case of poor control signal integrity. figure 20 . control pin interface for signal integrity stby epad 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 control circuit 2 pf 4. 7 kohm digital pin voltage and resistance values table 8 provides the open-circuit dc voltage referenced to ground and resistance value for the control pin listed. table 8. digital pin voltages and resistance pin name open circuit dc voltage internal connection 8 stby 0v 580k? resistor to ground
? 2018 integrated device technology, inc. 15 rev o may 11 , 2018 F1421 datasheet package drawings the package outline drawings are appended at the end of this document and are accessible from the link below. the package information is the most current data available. https://www.idt.com/document/psc/nlnlg24p1 -package-outline- 40 -x- 40 - mm -body- 05 - mm - pitch - qfn -epad-size- 245 -x-245- mm ordering information orderable part number package msl rating carrier type temperature F1421 nlgk 4mm x 4mm x 0.9mm 24 -pin qfn 1 tray -40 to +105c F1421 nlgk8 4mm x 4mm x 0.9mm 24 -pin qfn 1 reel -40 to +105c F1421evbi evaluation board marking diagram idtf 14 21 nlgk za 721ftg line 1 and 2 are the part number. line 3 z a is for die version. line 3 721 is one digit for the year and week that the part was assembled. line 3 ftg denotes the production process.
? 2018 integrated device technology, inc. 16 rev o may 11 , 2018 F1421 datasheet revision history revision revision date description of change o may 11, 2018 initial release. corporate headquarters 6024 silver creek valley road san jose, ca 95138 www.idt.com sales 1- 800 -345-7015 or 408- 284 -8200 fax: 408- 284 -2775 www.idt.com/go/sales tech support www.idt.com/go/support disclaimer integrated device technology, inc. (idt) and its affiliated companies (her ein referred to as idt) reserve the right to modify the products and/or specificatio ns described herein at any time, without notice, at idt's sole discretion. performance spe cifications and operating parameters of the described p roducts are determined in an independent state and a re not guaranteed to perform the same way when installed in customer products. the informati on contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not l imited to, the suitability of idt's products for any particular purpose, an implie d warranty of merchantability, or non -infringement of t he intellectual property rights of others. this docume nt is presented o nly as a guide and does not convey any license under intellectual property rights of idt or any third parties. idt's products are not intended for use in applicati ons involving extreme environmental conditions or in life support systems or similar devices where the failu re or malfunction of an idt product can be reasonably expected to significantly affect the health o r safety of users. anyone using an idt product in such a manner does so at their own risk, absent an expres s, written agreement by idt. integrated device technology, idt and the idt logo are trademarks or registered trademarks of idt and its subsidiaries in the uni ted states and other coun tries. other trademarks used herein are the property of idt or their respective third party owners. for d atasheet type definitions and a glossary of common terms, vi sit www.idt.com/go/glossary . all contents of this document are copyright of integrated device technology, inc. all rights reserved.

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